1. Field of the Invention
The invention relates generally to semiconductor memory devices, and more particularly, to a semiconductor memory device including a plurality of memory blocks each having redundancy memory cells for sharing. The invention has particular applicability to static random access memories (SRAMs).
2. Description of the Background Art
A semiconductor memory such as a static random access memory (hereinafter referred to as an SRAM) and a dynamic random access memory (hereinafter referred to as a DRAM) has been conventionally provided with a redundancy circuit for improving the yield rate in production. When a defect exists in a manufactured semiconductor memory, the semiconductor memory is remedied by the function of the redundancy circuit. In other words, in a conventional semiconductor memory, a row or column including a defective memory cell is replaced with a predetermined spare row or column functionally.
In general, defects in a semiconductor memory tend to be generated in adjacent rows (or memory cell rows) in a memory cell array. For example, two word lines in two adjacent memory cell rows are shorted, bringing the two adjacent memory rows to the "defective" state. This means that it is often necessary to remedy two or more adjacent memory cell rows. The present invention also proceeds this tendency in a semiconductor memory, and provides a countermeasure for the remedy (the second and fourth embodiments which will be described hereinafter). Although the present invention can generally be applied to a semiconductor memory such as an SRAM, a DRAM and the like, a case where the present invention is applied to an SRAM will be described as an example.
FIG. 8 is a block diagram of an SRAM showing the background of the present invention. Referring to FIG. 8, an SRAM 500 includes n memory blocks BK0 to BKn-1, and a block selector circuit 532 for selecting a memory block to be accessed. One of memory blocks BK0 to BKn-1, for example, the memory block BK0, includes a memory cell array 1a, a redundancy memory cell row (RMC) 7a, a row decoder 503a, a redundancy row decoder (RRD) 550a, a bit line load circuit 17a connected to a bit line, a multiplexer 8a for selecting a bit line pair to be accessed, a sense amplifier 9a for reading data, and a write buffer 33a for writing data. In an example where the SRAM 500 has 4-megabit storage capacity, 64 memory blocks BK0 to BK63 in total are provided.
The SRAM 500 further includes a row address buffer 2 for receiving an externally applied row address signal RA, a column address buffer 5 for receiving an externally applied column address signal CA, a block address buffer 31 for receiving an externally applied block address signal BA, a column decoder 6 for decoding a column address signal Y applied from column address buffer 5, a data input buffer 13 for receiving input data Di, a data output buffer 10 for providing output data Do, and a read/write control circuit 16 for operating in response to an externally applied chip selecting signal CS and a read/write control signal RWC.
In the SRAM 500 shown in FIG. 8, a block address signal for selecting memory blocks BK0 to BKn-1 is externally applied through the block address buffer 31. However, some cases are known where a part of row address signals RA is used for selecting blocks.
The block selector circuit 532 provides block selecting signals BS0 to BSn-1 for selecting memory blocks BK0 to BKn-1 in response to a signal Z provided from the block address buffer 31. Block selecting signals BS0 to BSn-1 are applied to corresponding row decoders and sense amplifiers in corresponding memory blocks BK0 to BKn-1, respectively. The corresponding row decoders and sense amplifiers are operated in response to activated block selecting signals.
Ordinary access operation will now be described. When the memory block BK0, for example, is accessed, the activated block selecting signal BS0 is applied to a row decoder 503a and a sense amplifier 9a. In reading data, a memory cell, not shown, in the memory cell array 1a is designated by the row decoder 503a and the column decoder 6. A data signal stored in the designated memory cell is applied to the sense amplifier 9a through the multiplexer 8a. A data signal amplified by the sense amplifier 9a is provided as output data Do through the data output buffer 10.
In the write operation, input data Di is applied to the write buffer 33a through the data input buffer 13. Write buffer 33a applies the applied data signal to the memory cell array 1a through the multiplexer 8a in response to the activated block selecting signal BS0 and a control signal applied from the read/write control circuit 16. Therefore, the data signal is written in a memory cell designated by the row decoder 503a and the column decoder 6.
When it is found that some defect exists in one memory cell row in the memory cell array 1a, the defective memory cell is replaced with the redundancy memory cell row 7a functionally as described hereinafter. A defective memory cell address indicating the position of the defective memory cell row is programmed by selectively disconnecting a fuse (not shown) provided in the redundancy row decoder 550a. Therefore, when access is requested for a row having a defective memory cell, the redundancy memory cell row 7a is accessed in place of the defective memory cell row, because of the function of the redundancy row decoder 550a. In other words, the defective memory cell row is replaced with the redundancy memory cell row 7a electrically or functionally. Operation of these redundancy circuits for remedy of a defective memory cell will be described in detail later.
FIG. 9 is a schematic diagram of a circuit of the memory cell array 1a shown in FIG. 8. Referring to FIG. 9, for simplicity of depiction, only four memory cells 24a to 24d in the memory cell array 1a are shown. Memory cells 24a and 24c are connected between bit lines 20a and 20b. Memory cells 24b and 24d are connected between bit lines 21a and 21b.
The bit line load circuit 17a includes NMOS transistors 25a, 25b, 26a and 26b each connected between a power supply potential Vcc and a corresponding one of bit lines 20a, 20b, 21a and 21b. On the other hand, the multiplexer 8a includes NMOS transistors 27a, 27b, 28a and 28b connected between I/O line pair 29a, 29b and bit lines 20a, 20b, 21a and 21b. I/O line pair 29a and 29b are connected to an input of the sense amplifier 9a and an output of the write buffer 33a.
The row decoder 503a selectively activates one of word lines WL0 and WL1 connected to a memory cell to be accessed. Memory cells 24a and 24b connected to a word line WL0 configure a memory cell row. When the word line WL0 is activated, a memory cell row including memory cells 24a and 24b is accessed. On the other hand, the column decoder 6 activates one of column selecting signals Y0 and Y1 for selecting a memory cell column to be accessed. When the column selecting signal Y0, for example, is activated, a memory cell column including memory cells 24a and 24c is accessed, since transistors 27a and 27b are turned on.
FIG. 10 is a schematic diagram of a circuit showing one example of the memory cell shown in FIG. 9. Referring to FIG. 10, the memory cell MC1 (for example, 24a of FIG. 9) includes NMOS transistors 41a and 41b, resistances 43a and 43b as high resistance loads, and NMOS transistors 42a and 42b as access gates.
FIG. 11 is a schematic diagram of a circuit showing another example of the memory cell shown in FIG. 9. Referring to FIG. 11, the memory cell MC2 includes NMOS transistors 41a and 41b, PMOS transistors 44a and 44b operating as loads, and NMOS transistors 42a and 42b as access gates.
FIG. 12 is a timing chart far explaining read operation of the memory cell 24a shown in FIG. 9. Referring to FIG. 12, the abscissa indicates time, and the ordinate indicates potential (volt). Lines ADi indicate change of input signals of the row address buffer 2 and the column address buffer 5. Lines ADo indicate change of output signals of the row and column address buffers 2 and 5. Lines WL indicate change of the word line WL0 connected to the memory cell 24a. Lines I/O indicate change of the I/O line pair 29a and 29b. Lines SAo indicate change of the output voltage of the sense amplifier 9a. Lines Do indicate change of output signals of the data output buffer 10.
At time t0, an input address signal ADi is changed. Therefore, output signals ADo of the address buffers 2 and 5 are changed at time t1. At time t2, since the potential of the word line WL0 changes, a data signal stored in the memory cell 24a is transmitted to bit line pair 20a, 20b. In addition to this, since the column selecting signal Y0 provided from the column decoder 6 attains a high level, transistors 27a and 27b are turned on. Therefore, at time t3, the potential of I/O line pair 29a and 29b is changed.
At time t4, since the sense amplifier 9a is activated in response to a control signal applied from the read/write control circuit 16, a data signal is amplified by the sense amplifier 9a. Therefore, at time t5, an output signal Do of the data output buffer 10 is changed in accordance with data read out of the memory cell 24a.
FIG. 13 is a schematic diagram of the block selector circuit 532 shown in FIG. 8. Referring to FIG. 13, the block selector circuit 532 includes NAND gates 100a to 100d for selectively receiving two of signals Z0 and Z1 provided from the block address buffer 31 and their inverted signals /Z0 and /Z1, respectively, and inverters 101a to 101d. Although the SRAM 500 shown in FIG. 8 includes n memory blocks, for simplicity of depiction and description, the block selector circuit 532 shown in FIG. 13 shows a circuit for selecting one of four memory blocks. Input signals Z0,/Z0, Z1 and/Z1 can be obtained from lower two bits of the externally applied block address signal BA. Inverters 101a to 101d provide block selecting signals BS0 to BS3, respectively.
Operation of the block selector circuit 532 will now be described. A case where the memory block BK0 is selected will be described as an example. The block address signal BA designating the memory block BK0 is externally applied to the block address buffer 31 shown in FIG. 8. The block address buffer 31 provides low level signals Z0 and Z1, and high level signals /Z0 and /Z1. Therefore, only the NAND gate 100a shown in FIG. 13 provides a low level signal, while other NAND gates 100b, 100c and 100d provide high level signals. As a result, only the block selecting signal BS0 attains a high level (is activated), while other block selecting signals BS1 to BS3 are retained at a low level.
FIG. 14 is a block diagram of a circuit of the row decoder 503a and the redundancy row decoder 550a shown in FIG. 8. The circuit shown in FIG. 14 is only a portion of the circuit for accessing four memory cell rows and one redundancy memory cell row in the memory cell array 1a. It is pointed out that row decoders 503b and 503c and redundancy row decoders 550b and 550c provided in other memory blocks BK1 to BKn-1 shown in FIG. 8 have the same circuit configurations as those shown in FIG. 14.
Referring to FIG. 14, the row decoder 503a includes NAND gates 55a to 55d for selectively receiving signals X0 and X1 provided from the row address buffer 2 shown in FIG. 8 and their inverted signals /X0 and /X1, respectively, and inverters 56a to 56d. In addition, NAND gates 55a to 55d are connected to also receive the block selecting signal BS0 provided from the block selector circuit 532. Outputs of inverters 56a to 56d are connected to word lines WL0 to WL3, respectively. Input signals X0 and X1 and their inverted signals /X0 and /X1 can be obtained from lower two bits of the externally applied row address signal RA.
The redundancy row decoder 550a includes a redundancy enable circuit 51 for activating the redundancy row decoder 550a itself, address program circuits 52a and 52b for programming a defective row address defining a memory cell row having a defective memory cell, an NAND gate 55e, and an inverter 56e. An output of the inverter 56e is connected to a word line WLR for accessing a redundancy memory cell row (which corresponds to the circuit 7a shown in FIG. 8). The NAND gate 55e is connected to receive redundancy enable signals RE, Sa and Sb provided from the redundancy enable circuit 51, address program circuits 52a and 52b, respectively, and the block selecting signal BS0.
FIG. 15 is a schematic diagram of the redundancy enable circuit. The redundancy enable circuit 51 shown in FIG. 14 can be implemented by the circuit 51 shown in FIG. 15. Referring to FIG. 15, the redundancy enable circuit 51 includes a capacitor 71, a resistance 72, and a PMOS transistor 74 connected in parallel between a power supply potential Vcc and a node 70, a fuse 73 for a program connected between the node 70 and the ground, and cascaded inverters 75 and 76.
When the redundancy circuit is used, that is, when a defective memory cell exists in the memory cell array, the fuse 73 is disconnected. Therefore, since the node 70 is retained at a high level, i.e., the power supply potential Vcc, a high level redundancy enable signal RE is provided through the inverter 76. On the other hand, when the redundancy circuit is not used, that is, when no defective memory cell exists in the memory cell array, the fuse 73 is not disconnected. Therefore, since the potential of the node 70 is retained at a low level, i.e., the ground level, a low level redundancy enable signal RE is provided.
FIG. 16 is a schematic diagram of an address program circuit. Address program circuits 52a and 52b shown in FIG. 14 can be implemented by using the circuit 52 shown in FIG. 16. Referring to FIG. 16, the address program circuit 52 includes a capacitor 61, a resistance 62, and a PMOS transistor 64 connected in parallel between the power supply potential Vcc and a node 60, a fuse 63 for a program connected between the node 60 and the ground, cascaded inverters 65 and 66, and two CMOS transmission gates TG1 and TG2. The transmission gate TG1 passes an input signal /X in response to the potential of a node 67. On the other hand, the transmission gate TG2 passes an input signal X in response to the potential of the node 67. One of input signals X and /X is provided as an output signal S in response to connection or disconnection of the fuse 63.
In operation, when the fuse 63 is disconnected, the potential of the node 60 is retained at a high level. Since, the potential of the node 67 is fixed at a level lower than that of the inverter 65, the transmission gate TG2 is turned on, causing the input signal X to be transmitted as an output signal S. Conversely, when the fuse 63 is connected, since the potential of the node 60 is retained at a low level, the potential of the node 67 is retained at a high level. Therefore, the transmission gate TG1 is turned on, whereby the input signal /X is transmitted as an output signal S.
Description will be given hereinafter of operation of the redundancy row decoder 550a shown in FIG. 14 to which circuits shown in FIGS. 15 and 16 are applied. Description will be given first to a case where no defect memory cell exists in the memory cell array 1a, that is, where the redundancy memory cell row 7a is not accessed. In this case, a fuse in the redundancy enable circuit 51 (which corresponds to the fuse 73 shown in FIG. 15) is not disconnected. Therefore, the low level redundancy enable signal RE is applied to the NAND gate 55e. Since an output signal of the NAND gate 55e is retained at a high level, the inverter 56e provides a low level redundancy word line signal WLR, causing the redundancy memory cell row 7a not to be accessed.
NAND gates 55a to 55d in the row decoder 503a receive a high level output signal of the NAND gate 55e and a high level block selecting signal BS0. Therefore, NAND gates 55a to 55d selectively activate one of word lines WL0 to WL3 (that is, selectively bring it to a high level) in response to signals X0, /X0, X1 and /X1 applied from the row address buffer 2. Therefore, a memory cell row connected to the activated word line can be accessed.
When a defective memory cell exists in the memory cell array 1a, that is, when replacement by the defective memory cell row 7a is employed, a fuse in the redundancy enable circuit 51 is disconnected, causing the high level redundancy enable signal RE to be applied to the NAND gate 55e. In addition to this, a row having a defective memory cell, that is, a row address defining the defective memory cell row, is programmed by selectively disconnecting fuses in address program circuits 52a and 52b.
Assuming that a defective memory cell exists in a memory cell row connected to the word line WL0, a program for defining this memory cell row is carried out. In other words, in respective address program circuits 52a and 52b, the program is carried out by leaving the corresponding fuse 63 connected. As a result, the address program circuit 52a provides the input signal /X0 as output signal Sa. On the other hand, the address program circuit 52b provides the input signal /X1 as output signal Sb. In both cases, when high level input signals /X0 and X1 are applied, high level output signals Sa and Sb are applied to the NAND gate 55e. As a result, since the NAND gate 55e provides a low level signal, the inverter 56e provides the high level redundancy word line signal WLR. The redundancy memory cell row 7a is accessed in response to the high level redundancy word line signal WLR. In addition to this, since a low level output signal of the NAND gate 55e is applied also to the NAND gate 55 a, the NAND gate 55a is disabled. In other words, the memory cell row connected to the word line WL0 cannot be accessed at this time.
As another example, when a defective memory cell exists in the memory cell row connected to the word line WL1, the corresponding fuse 63 in the address program circuit 52a is disconnected, and the corresponding fuse 63 in the address program circuit 526 is left connected. As a result, the NAND gate 55e is enabled when high level signals X0 and /X1 are applied, thereby activating the redundancy word line WLR.
In the above description, although programming for selecting one of four memory cell rows has been described, a number of memory cell rows are included in the memory cell array 1a in practice. Therefore, it is pointed out that address program circuits can be additionally provided in accordance with the number of memory cell rows.
As described above, a redundancy row decoder, for example, 550a can be used only for remedying a defective memory cell row which exists in the memory cell array 1a of one memory block BK0. In other words, referring to FIG. 8, although the redundancy memory cell row 7a in the memory cell block BK0 can be replaced with a defective memory cell row in the memory cell array 1a electrically or functionally, the redundancy memory cell row 7a cannot remedy a defective memory cell row which exists in the memory cell array 1b of another memory block, for example, BK1.
From the viewpoint of high integration, a conventional SRAM is generally provided with one or two redundancy memory cells or columns for a memory cell array. This means that when more than two defective memory cell rows or columns exist in one memory cell array, it is impossible to remedy them. Statistically, a defective portion in a semiconductor memory tends to be concentrated in one memory block. However, since only one or two redundancy memory cell rows or columns per a memory block were provided, it was difficult to effectively remedy many defective semiconductor memories. Therefore, SRAMs which are not remedied were to be discarded, causing lowering of the yield rate in production of semiconductor memories.